Basic design of a 6502 SBC
We propose a minimal design for a 6502 that includes SRAM and ROM but without I/O circuits. The design criteria is here below and a circuit schematic can be found as attachment at the end of the page.
Clock circuit
We use two inverter oscillator circuit also known as Hegener oscillator. Schematic of such oscillator can be found in the Synertek datasheet for 6502 (Synertek 6502 datasheet). The single-phase output of the oscillator is connected to the Phi0 (pin 37) of the 6502.
Reset circuit
The RESET pin on the 6502 is used to initiate an initialization sequence to reset the CPU. The sequence is started when RESET receives a positive going edge after being held LOW. The sequence's duration is six clock cycles and results in the interrupt flag being set and the CPU will load the program counter from memory locations $FFFC and $FFFD which must contain the memory location pointing to beginning of a program. In a power-up routine after the VCC reaches 4.75V, reset must be held LOW for at least two clock cycles. When RESET receives positive-going edge after at least two clock cycles the CPU will proceed with the initialization sequence.
To satisfy above requirements, for both the power-up sequence and to reset the computer without having to power cycle, we use a simple RC-circuit with a Schmitt trigger and an inverter. The circuit also serves as a debouncer for the RESET button.
Memory map
We are facing several constraints in how we plan to use the 6502's address space.
- Zero-page addressing is one of the 6502's addressing modes where if one only addresses using one byte, then the first address page ($0000-$00FF) is addressed.
- When the processor is resetted/started the 6502 loads the program counter from memory locations $FFFC and $FFFD.
We suggest the following memory map
| Device | Address range | Size |
|---|---|---|
| RAM | 0000 - $07FF | 32 KB |
| Screen | $8000-$9FFF | 8 KB |
| Port I/O | $A000-$BFFF | 8 KB |
| ROM | $C000-$FFFF | 16 KB |
R/W
The Microprocessor's signal wether the reading or writing operation is taking place. R/W (read operation = HIGH, write operation = LOW)
SRAM and writing to SRAM
As shown in the memory map we have allocated $0000-$7FFF for RAM, in total 32 KBytes and we select "SRM20256L a 32KB static-ram chip as our memory chip. We connect the chip's address lines A0-A14 and data lines D0-D7 to the CPU's address and data bus. The /CS (chip select) and /OE (output enable) pins we connect directly to the CPU's A15. Since /CS and /OE are active low, the chip is selected and it's data lines are enabled when A15 = LOW that corresponds to $0000-$7FFF.
The SRAM has usually three control inputs, /OE(output enable) for three-stating the data lines, /CS(chip select) and /WE (write enable) where the SRAM
becomes open for writing when asserted and the data inputs are latched into the selected memory location when /WE is negated. We can tie /OE and /CS
together since the output buffer of a RAM chip is three-stated anyway when in write cycle (/WE negated).
When it comes to writing to the RAM we might be tempted to connect the microprocessor's R/W directly to the RAM's /WE pin (Write enable, HIGH=Read, Low=Write). We will however implement /WE controlled write where /CS is asserted before /WE and when we are done writing we negate the /WE and subsequently we negate /CS. We control /CS by address decoding by directly connect /CS to the address line A15 of the 6502 and therefore is asserted in time TADS when the CPU addresses the SRAM and address lines are stable.
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| TADS | Address setup time | address inputs must be stable at this time before /WE is asserted, otherwise data stored at other locations could be corrupted. |
| TRWS | R/W setup time | The time it takes R/W to assert for write operation |
| TDS | Write data setup time | The data inputs must be stable at this time TDS=TPWHΦ2-TMDS before /WE is negated, otherwise the input data might not be correctly latched. |
| THW | Write data hold time | The data inputs must be stable for this time after /WE is negated and before /CS is negated. |
| TPWHΦ2 | High pulse width | This is the width of the write pulse, for how long /WE is negated. |
The SRAM is basically a D flip-flop working as a transparent latch with an edge sensitive clock input. By that the D-input is open to the output when the clock input is negated (LOW) and the input data is locked into the flip-flop on positive going clock edge. In any operation regarding a flip-flop the data must exist at the input for some time before and after the positive going edge. This is the data setup time (TDS) before the edge is positive going and the hold time (THW) after the edge operation has occurred.
We must as well account for a delay TADS for the 6502's address lines to become stable to select correct memory address; otherwise we could end up writing to incorrect memory addresses since unstable address lines would result in random memory location being selected and written too.
We can use the Φ2 clock phase to correctly time the write operation since we can observe in the 6502's data sheet that Φ2 clock is asserted before the data bus is activated and sufficient
time after the address bus has become stable. We therefore have that /WE = / ( /(R/W) xΦ2), i.e. we NAND the inverted R/W signal and Φ2 clock output.
ROM
We have allocated $C000-$FFFF for ROM, in total 16KBytes and we select the 27C128 EPROM from AMD as our ROM chip. We connect the chip's address lines A0-A13 and data lines D0-D7 to the CPU's address and data bus. We connect the /CE (chip enable) and /OE (output enable) pins together. When we address $C000-$FFFF we have the CPU's A14=A15=HIGH. Since /CE and /OE are active low, we have the chip selected when we NAND A14 and A15, i.e. /CS+/OE = /(A14 x A15).
NMI and IRQ
We tie the /NMI and /IRQ lines to the VCC for HIGH with a recommended 3KOhm resistor (see 6502 datasheet).
RDY
Used to halt the CPU on negative input edge, mainly when interfacing with low-speed ROM. We tie the RDY pin to high-state using 3KOhm resistor.
Circuit schematic and PCB
We have now completed the design of the basic design of an 6502 SBC and can now finalize it by making a circuit schematic of what we have proposed above. The basic design only covers the 6502, RAM, ROM and the clock. We have only covered I/O interfacing by assigning I/O to address range $A000-$BFFF. By that we have a quite modular design and the design and implementation of I/O circuits can therefor be adapted to whatever project we wish to use the SBC for. Since I/O has already been assigned a fixed address range in the memory map, we add a address decoded selection signal /IO_SELECT =/(/A14 x A15).
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6502 SBC printed circuit board (Eagle PCB, PDF COMPONENTS LAYOUT, PDF TOP, PDF BOTTOM)
| Bill of materials | |
|---|---|
| Part | Pcs. |
| 74LS00 | 1 |
| 74LS04 | 1 |
| 74LS14 | 1 |
| 2 MHz xtal | 1 |
| 3.3 kOhm | 4 |
| 1.5 kOhm | 1 |
| 15.0 kOhm | 1 |
| 1.0 kOhm | 1 |
| 680 Ohm | 1 |
| LED diode | 1 |
| 27C128 ROM | 1 |
| SRM256LC or compatible RAM | 1 |
| 6502 family microprocessor | 1 |